1. Field of the Invention
The present invention is directed to flash memory array structures.
2. Problem to be Solved
Memory devices typically comprise semiconductor memories organized in rectangular arrays of rows and columns on very-large-scale (VLSI) circuits. The intersection of one row and one column results in a storage element called a "cell". A semiconductor memory is comprised of a variety of such cells. Each cell is capable of storing a binary bit of data. Each column defines a bit line and each row is defines a word line. Addresses are assigned to each row or column. In order to write data into, or read data from, a row or column of cells, the desired address is provided in binary-coded form to the input of an address decoder. In response to the binary-coded input, the decoder selects the desired row or column for a write or read operation.
Memory devices such as flash memory arrays are typically comprised of an array configured with NAND-logic or NOR-logic. Such arrays are typically configured as a Manhattan-type structure. NAND-logic arrays have a density that is about twice that of NOR-logic arrays. However, access time is slow in NAND-logic arrays due to the series resistance through the circuitry. Furthermore, complex peripheral support circuits are required for NAND-Logic arrays. Additionally, NAND-logic arrays are limited to programming by Fowler-Nordheim tunneling which is a relatively slow process. Fowler-Nordheim tunneling requires the application of a relatively high voltage on unselected word lines to allow a full bit line bias potential to reach the far end or last device in the array without being reduced by numerous voltage drops (threshold voltage of each device in the chain). Thus, due to this high voltage applied to the unselected word lines, adjacent bit lines must be widely spaced apart thereby impeding the design of high-density memory arrays. NAND-Logic arrays are typically limited to 16 (sixteen) devices in series to avoid excessive series resistance. Furthermore, each memory cell of a NAND-Logic array requires two (2) extra select gates thereby increasing The manufacturing costs and decreasing the efficiency of NAN D-logic arrays.
Manhattan-type structured memory arrays typically utilize a long common diffusion shared by adjacent cells. Such a configuration is conducive to difficulties in programming and reading operations, e.g. reverse programming and read interference. For example, when a bit line is pulled down to a logic "low" level during sensing, it is not always clear whether the bit line is being pulled down by he selected cell or an adjacent cell. Similarly, when an addressed cell is in a non-conducting state, the corresponding selected bit line should be at a logic "high" level. However, the bit line may be erroneously pulled down to a logic "low" level by an adjacent unselected cell. Similar confusion results during programming operations. For example, programming an addressed cell may disturb an adjacent cell. There have been many attempts to solve these problems associated with programming and reading operations. One attempt involves designing each memory cell to have an unsymmetrical configuration. This is accomplished by angle-implanting in one direction of the memory cell so that disturbance from one direction is less than disturbance received from an opposite direction. However, it has been found that the aforementioned problems are only marginally reduced by such a cell configuration. Furthermore, unsymmetrical memory cell configurations require a relatively larger sized memory cell. Another attempt to solve the aforementioned problems is to provide an additional split-gate in order to eliminate the interference. However, this approach also increases the size of the memory cell. A further approach involves the separation of the drain diffusion for memory cells sharing the same word line.
NAND-Logic and NOR-logic memory arrays typically utilize multi-polysilicon layers configured in "stacks". However, parasitic capacitances result from overlay tolerances defined by the degree to which one layer overlaps another layer. If the layers overlap one another significantly, significant parasitic capacitances result which have a deleterious effect on the operation of the memory array.
Bearing in mind the problems and deficiencies of the conventional memory arrays, it is an object of the present invention to provide a memory array architecture that provides increased integration density without deteriorating the characteristics of the memory cells therein.
It is another object of the present invention to provide a memory array architecture that minimizes the peripheral component count.
It is a further object of the present invention to provide a memory array architecture that provides a relatively fast access time for read or write operations and which has a relatively low power consumption.
It a yet another object of the present invention to provide a memory array that comprises memory cells that can be programmed and read without causing interference to adjacent memory cells.
It is another object of the present invention to provide a memory array architecture that may be used to realize random-access memories as well as read-only-memories.
Other objects and advantages will be apparent to one of skill in the art from the following description.